LOCKUP=0, POR=0, CORE1=0, LOC=0, WDOG=0, WAKEUP=0, MDM_AP=0, LOL=0, LVD=0, SACKERR=0, SW=0, PIN=0
System Reset Status Register
| WAKEUP | VLLS Wakeup Reset 0 (0): Reset not caused by wakeup from VLLS mode. 1 (1): Reset caused by wakeup from VLLS mode. |
| LVD | Low-Voltage Detect Reset or High-Voltage Detect Reset 0 (0): Reset not caused by LVD trip, HVD trip or POR 1 (1): Reset caused by LVD trip, HVD trip or POR |
| LOC | Loss-of-Clock Reset 0 (0): Reset not caused by a loss of external clock. 1 (1): Reset caused by a loss of external clock. |
| LOL | Loss-of-Lock Reset 0 (0): Reset not caused by a loss of lock in the PLL 1 (1): Reset caused by a loss of lock in the PLL |
| WDOG | Watchdog 0 (0): Reset not caused by watchdog timeout 1 (1): Reset caused by watchdog timeout |
| PIN | External Reset Pin 0 (0): Reset not caused by external reset pin 1 (1): Reset caused by external reset pin |
| POR | Power-On Reset 0 (0): Reset not caused by POR 1 (1): Reset caused by POR |
| LOCKUP | Core Lockup 0 (0): Reset not caused by core LOCKUP event 1 (1): Reset caused by core LOCKUP event |
| SW | Software 0 (0): Reset not caused by software setting of SYSRESETREQ bit 1 (1): Reset caused by software setting of SYSRESETREQ bit |
| MDM_AP | MDM-AP System Reset Request 0 (0): Reset was not caused by host debugger system setting of the System Reset Request bit 1 (1): Reset was caused by host debugger system setting of the System Reset Request bit |
| SACKERR | Stop Acknowledge Error 0 (0): Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 1 (1): Reset caused by peripheral failure to acknowledge attempt to enter stop mode |
| CORE1 | Core 1 Reset 0 (0): Reset not caused by Core 1 Reset Source. 1 (1): Reset caused by Core 1 Reset Source. |